硕士生导师 陈功 简介
【个人简介】
陈功，男，副研究员，博士研究生学历，博士（后）学位。现任154.com皇冠（微电子学院）集成电路教研室主任。2015年博士毕业于日本北九州市立大学，2018年日本早稻田大学特聘研究员。
陈功博士于 2017 年获得成都市高层次人才，2018 年获得蓉漂计划特聘专家。主要研究方向包括电源管理IC、高速、高精度 AD/DA 转换器以及SoC系统等，在信号采集处理SoC、生物电子交叉学科等方向有比较深入的研究和成果转化。目前已发表学术论文二十余篇，正在申报和已经授权的专利十余项，主持或参与多项研究项目和教改项目。
【研究方向】
1.数模混合设计
2.物理设计
【主持（研）项目】
1. 国家xxx基金，基于xxx高速高精度ADC设计，在研，项目负责人；
2. 国家xxx专项，xxx射频通道设计研究，在研，课题负责人；
3. 国家自然科学基金委（青年），研究用于脑电信号获取系统的多通道有源电极的专用集成芯片，已结题，项目负责人；
4. 国家博士后面上二等资助，研究脑电信号获取设备的多通道有源电极ASIC关键技术，已结题，项目负责人；
5. 四川省人社厅归国留学人员创新项目，关于可穿戴脑波信号多通道数字化主动式电极芯片IP设计的可行性研究，已结题，项目负责人；
6. 成都市委组织部成都高层次人才创业项目C类，研发大功率无线充电方案与芯片，已结题，项目负责人；
7. 四川省教育厅科研计划，采样模拟补偿PWM可调反激式LDO研发，已结题，项目负责人；
8. 横向项目，多通道数据采集处理SoC芯片研制等，4项，已结题或在研，项目负责人；
9. 成都信息工程大学中青年学术带头人基金，生物电信号采集前端关键技术研制，结题，项目负责人。
【发表论文】
[1] G. Chen et al., "Analog Triggered Asynchronous Clocking Technique Based on the Ring Amplifier in Pipeline ADC," International Conference on Computer and Communications (ICCC 2022), Chengdu, 2022.
[2] G. Chen et al., "A Linearity Bootstrapped Switch with Dynamic Bulk Biasing Design for CMOS Image Sensors," International Conference on Sensing and Imaging (ICSI 2017), Chengdu, 2017, pp. 105-115.
[3] G. Chen et al., "A 9-bit 10MSps SAR ADC with double input range for supply voltage," 2017 IEEE 17th International Conference on Communication Technology (ICCT), Chengdu, 2017, pp. 1786-1790.
[4] G. Chen, B. Liu, S. Nakatake and B. Yang, "Routability of twisted common-centroid capacitor array under signal coupling constraints," 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016, pp. 1-4.
[5] Bo Liu, Gong Chen, Bo Yang, and Shigetoshi Nakatake. 2018. Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Des. Autom. Electron. Syst. 23, 4, Article 47 (June 2018), 17 pages.
[6] Weiwei Ling, Gong Chen, Peng Lei, Yao Yao, Li Li, Yao Huang, Hua Wei, Jiang Du, Low-firing behavior, microstructure, and electromagnetic properties of a ferroelectric-ferromagnetic composite material with multiple doping, Journal of Alloys and Compounds, Volume 750, 2018, Pages 479-489.
[7] Kun Mao, Hai Shi Wang, Yao Yao, Hai Nie, Gong Chen et al., "A 500-V High ON-BV Parasitic JFET With an Optimized Drift Region,"IEEE Transactions on Electron Devices Volume: 66, Issue: 3, March 2019
[8] Li, Li Alex, Wei Hua, Yao Yao, Gong Chen, Weiwei Ling, Jiang Du, Yao Huang, Multi-segmental OFDM signals equalization with piecewise linear channel model over rapidly time-varying channels, EURASIP Journal on Wireless Communications and Networking, 2017, Article number: 191.
[9] Juan Zhou, Ying Shen, Gong Chen, "Analysis of RF Channel Isolation Impact in Wireless Co-Time Co-Frequency Full Duplex," 2017 IEEE 17th International Conference on Communication Technology (ICCT), Chengdu, 2017, pp. 131-139.
[10] Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake. Layout Dependent Effect-aware Leakage Current Reduction and Its Application to Low-power SAR-ADC. IEICE Transaction on Fundamentals of Electronics, Communication and Computer Sciences, July, 2015 (SCI)
[11] Gong Chen, TORU Fujimura, Qing Dong, SHIGETOSHI Nakatake, Bo Yang. DC Characteristics and Variability on 90nm CMOS Transistor Array-style Analog Layout. ACM Transactions on Design Automation of Electronic Systems. Accepted.（SCI）
[12] Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Ming-Yu Li,SHIGETOSHI Nakatake . Analog Circuit Synthesis with Constraint Generation of Layout Dependent Effects by Geometric Programming. IEICE Transaction on Fundamentals of Electronics, Communication and Computer Sciences，Dec., 2013.（SCI）
[13] Ming-Yu Li, Chuan Li, Gong Chen, Yu Zhang, Qing Dong, SHIGETOSHI Nakatake. A New Sparse Design Framework for Broadband Power Amplifier Behavioral Modeling and Digital Predistortion. IEEJ Trans Elec Electron Eng, June, 2014（SCI）
[14] Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue. A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.Circuits and Systems (ISCAS)，May，2012
[15] Gong Chen, Zhang Yu, Bo Yang, Qing Dong, Shigetoshi Nakatake. A comparator energy model considering shallow trench isolation stress by geometric programming. Quality Electronic Design (ISQED)， March，2013
[16] Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake. A 9-bit 50MSps SAR ADC with Pre-charge VCM –based Double Input Range Algorithm. Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI，May，2013
[17] Gong Chen, Qing Dong, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue. A Novel Retargeting Methodology in Computer Aided Design of Nano-watt CMOS Reference Circuit based on Advanced Compact MOSFET Model. Journal of Computational Information Systems, March, 2015（EI）
[18] Yu Zhang, Gong Chen, Qing Dong, Ming-Yu Li, Shigetoshi Nakatake. Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects, Very Large Scale Integration (VLSI-SoC), Non., 2013
[19] Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake. Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. Quality Electronic Design (ISQED)， March，2012
[20] 陳功, 陰徳龍, 楊波, 董青, 李静, 中武繁寿.CMOSナノワットBGR回路のプロセス移行の制約再利用に関する考察, 電子情報通信学会技術研究報告.VLD, VLSI設計技術. March，2011
[21] 陳功, 張宇, 楊波, 董青, 中武繁寿. GP最適化法に基づくSTI制約を考慮したコンパレータ回路エネルギーモデルの提案,電子情報通信学会技術研究報告. VLD, VLSI設計技術. Aug. 2012
[22] 陳功, 張宇, 楊波, 董青, 李明玉, 中武繁寿.リーク電流抑制を伴う低電力設計方式による9bit, 20MS/s SAR ADC設計.電子情報通信学会技術研究報告.VLD, VLSI設計技術. Non. 2013
[23] Gong Chen, Zhang Yu, Mingyu Li, Qing Dong, Shigetoshi Nakatake. A Linearity Bootstrapped Switch with Dynamic Bulk Biasing Design. 第26回 回路とシステムワークショップ, July. 2013
[24] Ming-Yu Li, Gong Chen, Yu Zhang, Qing Dong, SHIGETOSHI Nakatake. Simplified Compressed Sensing-Based Volterra Model for Broadband Wireless Power Amplifiers，第26回 回路とシステムワークショップ, July. 2013
[25] 陳功, 張宇, 楊波, 董青, 李静, 中武繁寿. A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage,電子情報通信学会技術研究報告. VLD, VLSI設計技術, Non. 2011
[26] 陳功, 陰徳龍, 楊波, 董青, 李静, 中武繁寿. CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects,電子情報通信学会技術研究報告. VLD, VLSI設計技術, Sep. 2012
【授权专利】
[1] 一种双绞式共用中心电容阵列及其版图设计方法，实用新型专利，201710791860.5，已授权。
[2] 一种集成程控增益放大功能的模拟前端结构，实用新型专利，201922056997.3，已授权。
[3] 过压保护用电流比较电路，实用新型专利，202021119940.X，已授权。
[4] 一种用于流水线ADC的全差分放大器，实用新型专利，申请号：202020747886.7，已授权。
[5] 一种自校准复合结构ADC，实用新型专利，申请号：202021115641.9，已授权
【联系方式】
电子邮件：chg@cuit.edu.cn
